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Hosoi, Takuji*; Osako, Momoe*; Moges, K.*; Ito, Koji*; Kimoto, Tsunenobu*; Sometani, Mitsuru*; Okamoto, Mitsuo*; Yoshigoe, Akitaka; Shimura, Takayoshi*; Watanabe, Heiji*
Applied Physics Express, 15(6), p.061003_1 - 061003_5, 2022/06
Times Cited Count:2 Percentile:32.25(Physics, Applied)The combination of NO annealing and subsequent post-nitridation annealing (PNA) in CO ambient for SiO/SiC structures has been demonstrated to be effective in obtaining both high channel mobility and superior threshold voltage stability in SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs). N atoms on the SiO side of the SiO/SiC interface incorporated by NO annealing, which are plausible cause of charge trapping sites, could be selectively removed by CO-PNA at 1300C without oxidizing the SiC. CO-PNA was also effective in compensating oxygen vacancies in SiO, resulting high immunity against both positive and negative bias-temperature stresses.
Oshima, Takeshi; Uedono, Akira*; Ito, Hisayoshi; Abe, Koji*; Suzuki, Ryoichi*; *; Aoki, Yasushi; Tanigawa, Shoichiro*; Yoshikawa, Masahito; Mikado, Tomohisa*; et al.
Mater. Sci. Forum, 264-268, p.745 - 748, 1998/00
no abstracts in English